Floating gate structures

ABSTRACT

Structures and methods for DEAPROM memory with low tunnel barrier intergate insulators are provided. The DEAPROM memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZrO 2 , Nb 2 O 5 , Y 2 O 3 , Gd 2 O 3 , SrBi 2 Ta 2 O 3 , SrTiO 3 , PbTiO 3 , and PbZrO 3 . The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a continuation of U.S. application Ser. No.11/212,190, filed on Aug. 26, 2005; which is a divisional of U.S.application Ser. No. 10/789,038, filed on Feb. 27, 2004, now issued asU.S. Pat. No. 7,027,328; which is a divisional of U.S. application Ser.No. 09/945,498, filed on Aug. 30, 2001, now issued as U.S. Pat. No.6,778,441; each of which is incorporated herein by reference.

This application is related to the following commonly assigned U.S.patent applications: “DRAM Cells with Repressed Memory Metal OxideTunnel Insulators,” Ser. No. 09/945,395, now issued as U.S. Pat. No.6,754,108; “Programmable Array Logic or Memory Devices with AsymmetricalTunnel Barriers,” Ser. No. 09/943,134, now issued as U.S. Pat. No.7,042,043; “Flash Memory with Low Tunnel Barrier Interpoly Insulators,”Ser. No. 09/945,507, now issued as U.S. Pat. No. 7,068,544; “FieldProgrammable Logic Arrays with Metal Oxide and/or Low Tunnel BarrierInterpoly Insulators,” Ser. No. 09/945,512, now issued as U.S. Pat. No.7,087,954; “SRAM Cells with Repressed Floating Gate Memory, Metal OxideTunnel Interpoly Insulators,” Ser. No. 09/945,554, now issued as U.S.Pat. No. 6,963,103; and “Programmable Memory Address and Decode Deviceswith Low Tunnel Barrier Interpoly Insulators,” Ser. No. 09/945,500, nowissued as U.S. Pat. No. 7,075,829; which were filed on Aug. 30, 2001,and each of which disclosure is herein incorporated by reference.

FIELD OF THE INVENTION

The present invention relates generally to integrated circuits, and inparticular to programmable memory with low tunnel barrier interpolyinsulators which require refresh.

BACKGROUND OF THE INVENTION

Flash memories have become widely accepted in a variety of applicationsranging from personal computers, to digital cameras and wireless phones.Both INTEL and AMD have separately each produced about one billionintegrated circuit chips in this technology.

The original EEPROM or EARPROM and flash memory devices described byToshiba in 1984 used the interpoly dielectric insulator for erase. (Seegenerally, F. Masuoka et al., “A new flash EEPROM cell using triplepolysilicon technology,” IEEE Int. Electron Devices Meeting, SanFrancisco, pp. 464-67, 1984; F. Masuoka et al., “256K flash EEPROM usingtriple polysilicon technology,” IEEE Solid-State Circuits Conf.,Philadelphia, pp. 168-169, 1985). Various combinations of silicon oxideand silicon nitride were tried. (See generally, S. Mori et al.,“reliable CVD inter-poly dialectics for advanced E&EEPROM,” Symp. OnVLSI Technology, Kobe, Japan, pp. 16-17, 1985). However, the rough topsurface of the polysilicon floating gate resulted in, poor qualityinterpoly oxides, sharp points, localized high electric fields,premature breakdown and reliability problems.

Widespread use of flash memories did not occur until the introduction ofthe ETOX cell by INTEL in 1988. (See generally, U.S. Pat. No. 4,780,424,“Process for fabricating electrically alterable floating gate memorydevices,” 25 Oct. 1988; B. Dipert and L. Hebert, “Flash memory goesmainstream,” IEEE Spectrum, pp. 48-51, October, 1993; R. D. Pashley andS. K. Lai, “Flash memories, the best of two worlds,” IEEE Spectrum, pp.30-33, December 1989). This extremely simple cell and device structureresulted in high densities, high yield in production and low cost. Thisenabled the widespread use and application of flash memories anywhere anon-volatile memory function is required. However, in order to enable areasonable write speed the ETOX cell uses channel hot electroninjection, the erase operation which can be slower is achieved byFowler-Nordheim tunneling from the floating gate to the source. Thelarge barriers to electron tunneling or hot electron injection presentedby the silicon oxide-silicon interface, 3.2 eV, result in slow write anderase speeds even at very high electric fields. The combination of veryhigh electric fields and damage by hot electron collisions in the oxideresult in a number of operational problems like soft erase error,reliability problems of premature oxide breakdown and a limited numberof cycles of write and erase.

Other approaches to resolve the above described problems include; theuse of different floating gate materials, e.g. SiC, SiOC, GaN, andGaAIN, which exhibit a lower work function (see FIG. 1A), the use ofstructured surfaces which increase the localized electric fields (seeFIG. 1B), and amorphous SiC gate insulators with larger electronaffinity, χ, to increase the tunneling probability and reduce erase time(see FIG. 1C).

One example of the use of different floating gate (FIG. 1A) materials isprovided in U.S. Pat. No. 5,801,401 by L. Forbes, entitled “FLASH MEMORYWITH MICROCRYSTALLINE SILICON CARBIDE AS THE FLOATING GATE STRUCTURE.”Another example is provided in U.S. Pat. No. 5,852,306 by L. Forbes,entitled “FLASH MEMORY WITH NANOCRYSTALLINE SILICON FILM AS THE FLOATINGGATE.” Still further examples of this approach are provided in pendingapplications by L. Forbes and K. Ahn, entitled “DYNAMIC RANDOM ACCESSMEMORY OPERATION OF A FLASH MEMORY DEVICE WITH CHARGE STORAGE ON A LOWELECTRON AFFINITY GaN OR GaAIN FLOATING GATE,” Ser. No. 08/908,098, and“VARIABLE ELECTRON AFFINITY DIAMOND-LIKE COMPOUNDS FOR GATES IN SILICONCMOS MEMORIES AND IMAGING DEVICES,” Ser. No. 08/903,452.

An example of the use of the structured surface approach (FIG. 1B) isprovided in U.S. Pat. No. 5,981,350 by J. Geusic, L. Forbes, and K. Y.Ahn, entitled “DRAM CELLS WITH A STRUCTURE SURFACE USING A SELFSTRUCTURED MASK.” Another example is provided in U.S. Pat. No. 6,025,627by L. Forbes and J. Geusic, entitled “ATOMIC LAYER EXPITAXY GATEINSULATORS AND TEXTURED SURFACES FOR LOW VOLTAGE FLASH MEMORIES.”

Finally, an example of the use of amorphous SiC gate insulators (FIG.1C) is provided in U.S. patent application Ser. No. 08/903,453 by L.Forbes and K. Ahn, entitled “GATE INSULATOR FOR SILICON INTEGRATEDCIRCUIT TECHNOLOGY BY THE CARBURIZATION OF SILICON.”

Additionally, graded composition insulators to increase the tunnelingprobability and reduce erase time have been described by the sameinventors. (See, L. Forbes and J. M. Eldridge, “GRADED COMPOSITION GATEINSULATORS TO REDUCE TUNNELING BARRIERS IN FLASH MEMORY DEVICES,”application Ser. No. 09/945,514.

The authors of the present invention have also previously described theconcept of a programmable read only memory which requires refresh or isvolatile as a consequence of leakage currents though gate dielectricswith a low tunnel barrier between a floating gate and the siliconsubstrate/well, transistor source, drain, and body regions. (Seegenerally, L. Forbes, J. Geusic and K. Ahn, “DEAPROM (DynamicElectrically Alterable Programmable Read Only Memory) UTILIZINGINSULATING AND AMORPHOUS SILICON CARBIDE GATE INSULATOR,” applicationSer. No. 08/902,843). An application relating to leakage currentsthrough an ultrathin gate oxide has also been provided. (See generally,L. Forbes, E. H. Cloud, J. E. Geusic, P. A. Farrar, K. Y. Ahn, and A. R.Reinberg; and D. J. McElroy, and L. C. Tran, “DYNAMIC FLASH MEMORY CELLSWITH ULTRATHIN TUNNEL OXIDES,” U.S. Pat. No. 6,249,460).

However, all of these approaches relate to increasing tunneling betweenthe floating gate and the substrate such as is employed in aconventional ETOX device and do not involve tunneling between thecontrol gate and floating gate through an inter-poly dielectric.

Therefore, there is a need in the art to provide improved DEAPROM cellswhich increase memory densities while avoiding the large barriers toelectron tunneling or hot electron injection presented by the siliconoxide-silicon interface, 3.2 eV, which result in slow write and erasespeeds even at very high electric fields. There is also a need to avoidthe combination of very high electric fields and damage by hot electroncollisions in the which oxide result in a number of operational problemslike soft erase error, reliability problems of premature oxide breakdownand a limited number of cycles of write and erase. Further, when usingan interpoly dielectric insulator erase approach, the above mentionedproblems of having a rough top surface on the polysilicon floating gatewhich results in, poor quality interpoly oxides, sharp points, localizedhigh electric fields, premature breakdown and reliability problems mustbe avoided.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1C illustrate a number of previous methods for reducingtunneling barriers in DEAPROM memory.

FIG. 2 illustrates one embodiment of a floating gate transistor, orDEAPROM memory cell, according to the teachings of the presentinvention.

FIG. 3 illustrates another embodiment of a floating gate transistor, orDEAPROM memory cell, according to the teachings of the presentinvention.

FIG. 4 is a perspective view illustrating an array of silicon pillarsformed on a substrate as used in one embodiment according to theteachings of the present invention.

FIGS. 5A-5E are cross sectional views taken along cut line 5-5 from FIG.4 illustrating a number of floating gate and control gate configurationswhich are included in the scope of the present invention.

FIGS. 6A-6D illustrate a number of address coincidence schemes can beused together with the present invention.

FIG. 7A is an energy band diagram illustrating the band structure atvacuum level with the low tunnel barrier interpoly insulator accordingto the teachings of the present invention.

FIG. 7B is an energy band diagram illustrating the band structure duringan erase operation of electrons from the floating gate to the controlgate across the low tunnel barrier interpoly insulator according to theteachings of the present invention.

FIG. 7C is a graph plotting tunneling currents versus the appliedelectric fields (reciprocal applied electric field shown) for a numberof barrier heights.

FIG. 8 is an energy band diagram illustrating work function, tunnelbarrier heights and electron affinities for a low tunnel barrierintergate insulator according to the teachings of the present invention.

FIG. 9 illustrates a block diagram of an embodiment of an electronicsystem according to the teachings of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following detailed description of the invention, reference ismade to the accompanying drawings which form a part hereof, and in whichis shown, by way of illustration, specific embodiments in which theinvention may be practiced. The embodiments are intended to describeaspects of the invention in sufficient detail to enable those skilled inthe art to practice the invention. Other embodiments may be utilized andchanges may be made without departing from the scope of the presentinvention. In the following description, the terms wafer and substrateare interchangeably used to refer generally to any structure on whichintegrated circuits are formed, and also to such structures duringvarious stages of integrated circuit fabrication. Both terms includedoped and undoped semiconductors, epitaxial layers of a semiconductor ona supporting semiconductor or insulating material, combinations of suchlayers, as well as other such structures that are known in the art.

The term “horizontal” as used in this application is defined as a planeparallel to the conventional plane or surface of a wafer or substrate,regardless of the orientation of the wafer or substrate. The term“vertical” refers to a direction perpendicular to the horizontal asdefined above. Prepositions, such as “on”, “side” (as in “sidewall”),“higher”, “lower”, “over” and “under” are defined with respect to theconventional plane or surface being on the top surface of the wafer orsubstrate, regardless of the orientation of the wafer or substrate. Thefollowing detailed description is, therefore, not to be taken in alimiting sense, and the scope of the present invention is defined onlyby the appended claims, along with the full scope of equivalents towhich such claims are entitled.

The present invention describes the use of an ultra-thin metal oxideinter-poly dielectric insulators having a tunnel barrier of less than1.5 eV between the control gate and the floating gate. As shown in FIG.2, the ultra-thin metal oxide inter-poly dielectric insulators having atunnel barrier of less than 1.5 eV are used to create a memory cellwhich has a high current gain, and is easy to program by tunneling butwhich requires refresh. The low barrier tunnel insulator between thefloating gate and control gates makes erase of the cell easy but resultsin the requirement for refresh. One possible array structure is shown inFIG. 6A, described in more detail below. These devices of the presentinvention act like DRAM's and can be utilized as DRAM replacements. Inbrief, FIG. 6A illustrates that a coincident address is achieved byaddressing both the control gate address lines (y-address) and sourceaddress lines (x-address).

Also, as described in more detail below, FIG. 7A shows the conventionalsilicon oxide gate insulator with a high barrier and then the low tunnelbarrier interpoly or intergate insulator between the floating gate andthe control gate, as according to the present invention. According tothe teachings of the present invention, if the interpoly dielectric isthin enough, e.g. less than 20 Angstroms, or the barrier is low enough,e.g. less than 1.5 eV, to allow a very easy erase then there will besome finite leakage current when the device is addressed for readoperations and/or is in a standby state. This will require refresh ofthe memory state. The tunneling current in erasing charge from thefloating gate by tunneling to the control gate will then be as shown anddescribed below in FIG. 7C given by an equation of the form:J=B exp(−Eo/E)where E is the electric field across the interpoly dielectric insulator707 and Eo depends on the barrier height. Aluminum oxide has a currentdensity of 1 A/cm² at a field of about E=1V/20 Å=5×10⁺⁶ V/cm. Siliconoxide transistor gate insulators have a current density of 1 A/cm² at afield of about E=2.3V/23A=1×10⁺⁷ V/cm. The lower electric field in thealuminum oxide interpoly insulator for the same current density reflectsthe lower tunneling barrier of less than 2.0 eV as opposed to the 3.2 eVtunneling barrier of silicon oxide.

FIG. 7C, discussed below, illustrates the dependence of the tunnelingcurrents on electric field (reciprocal electric field) and barrierheight. Low barriers will result in high current densities at lowelectric fields during write and erase, however, they will also conductsome small but significant current during the electric fields employedfor read and as a consequence the data must be refreshed. These memorydevices work on a dynamic basis.

As stated above, the present invention describes the use of metal oxideinter-poly dielectric insulators between the control gate and thefloating gate. An example is shown in FIG. 2 for a planar structure, orhorizontal DEAPROM memory cell. According to the teachings of thepresent invention. The use of metal oxide films for this purpose offer anumber of advantages including:

(i) Flexibility in selecting a range of smooth metal film surfaces andcompositions that can be oxidized to form tunnel barrier insulators.

(ii) Employing simple “low temperature oxidation” to produce oxide filmsof highly controlled thickness, composition, purity and uniformity.

(iii) Avoiding inadvertent inter-diffusion of the metal and silicon aswell as silicide formation since the oxidation can be carried out atsuch low temperatures.

(iv) Using metal oxides that provide desirably lower tunnel barriers,relative to barriers currently used such as SiO₂.

(v) Providing a wide range of higher dielectric constant oxide filmswith improved capacitance characteristics.

(vi) Providing a unique ability to precisely tailor tunnel oxide barrierproperties for various device designs and applications.

(vii) Permitting the use of thicker tunnel barriers, if needed, toenhance device performance and its control along with yield andreliability.

(viii) Developing layered oxide tunnel barriers by oxidizing layeredmetal film compositions in order, for example, to enhance device yieldsand reliability more typical of single insulating layers.

(ix) Eliminating soft erase errors caused by the current technique oftunnel erase from floating gate to the source.

FIG. 2 illustrates one embodiment of a floating gate transistor, orDEAPROM memory cell 200, according to the teachings of the presentinvention. As shown in FIG. 2, the DEAPROM memory cell 200 includes afirst source/drain region 201 and a second source/drain region 203separated by a channel region 205 in a substrate 206. A floating gate209 opposes the channel region 205 and is separated therefrom by a gateoxide 211. A control gate 213 opposes the floating gate 209. Accordingto the teachings of the present invention, the control gate 213 isseparated from the floating gate 209 by a low tunnel barrier intergateinsulator 215 having a tunnel barrier height of less than 1.5 eV, andwhich requires refresh.

In one embodiment of the present invention, low tunnel barrier intergateinsulator 215 includes a metal oxide insulator selected from the groupconsisting of nickel oxide (NiO) and aluminum oxide (Al₂O₃) and having athickness of less than 20 Angstroms. In an alternative embodiment of thepresent invention, the low tunnel barrier intergate insulator 215includes a transition metal oxide and the transition metal oxide isselected from the group consisting of Ta₂O₅, TiO₂, ZrO₂, Nb₂O₅, Y₂O₃,and Gd₂O₃ having a tunnel barrier of less than 1.5 eV. In still anotheralternative embodiment of the present invention, the low tunnel barrierintergate insulator 215 includes a Perovskite oxide tunnel barrierselected from the group consisting of SrBi₂Ta₂O₃, SrTiO₃, PbTiO₃, andPbZrO₃ having a tunnel barrier of less than 1.5 eV.

According to the teachings of the present invention, the floating gate209 includes a polysilicon floating gate 209 having a metal layer 216formed thereon in contact with the low tunnel barrier intergateinsulator 215. Likewise, the control gate 213 includes a polysiliconcontrol gate 213 having a metal layer 217 formed thereon in contact withthe low tunnel barrier intergate insulator 215. In one embodiment, themetal layers 216 and 217, are formed of platinum (Pt). In an alternativeembodiment, the metal layers 216 and 217, are formed of aluminum (Al).

FIG. 3 illustrates another embodiment of a floating gate transistor, orDEAPROM memory cell 300, according to the teachings of the presentinvention.

As shown in the embodiment of FIG. 3, the DEAPROM memory cell 300includes a vertical non volatile memory cell 300. In this embodiment,the DEAPROM memory cell 300 has a first source/drain region 301 formedon a substrate 306. A body region 307 including a channel region 305 isformed on the first source/drain region 301. A second source/drainregion 303 is formed on the body region 307. A floating gate 309 opposesthe channel region 305 and is separated therefrom by a gate oxide 311. Acontrol gate 313 opposes the floating gate 309. According to theteachings of the present invention, the control gate 313 is separatedfrom the floating gate 309 by a low tunnel barrier intergate insulator315 having a tunnel barrier height of less than 1.5 eV, and whichrequires refresh.

In one embodiment of the present invention, low tunnel barrier intergateinsulator 315 includes a metal oxide insulator selected from the groupconsisting of nickel oxide (NiO) and aluminum oxide (Al₂O₃) and having athickness of less than 20 Angstroms. In an alternative embodiment of thepresent invention, the low tunnel barrier intergate insulator 315includes a transition metal oxide and the transition metal oxide isselected from the group consisting of Ta₂O₅, TiO₂, ZrO₂, Nb₂O₅, Y₂O₃,and Gd₂O₃ having a tunnel barrier of less than 1.5 eV. In still anotheralternative embodiment of the present invention, the low tunnel barrierintergate insulator 315 includes a Perovskite oxide tunnel barrierselected from the group consisting of SrBi₂Ta₂O₃, SrTiO₃, PbTiO₃, andPbZrO₃ having a tunnel barrier of less than 1.5 eV.

According to the teachings of the present invention, the floating gate309 includes a polysilicon floating gate 309 having a metal layer 316formed thereon in contact with the low tunnel barrier intergateinsulator 315. Likewise, the control gate 313 includes a polysiliconcontrol gate 313 having a metal layer 317 formed thereon in contact withthe low tunnel barrier intergate insulator 315. In one embodiment, themetal layers 316 and 317, are formed of platinum (Pt). In an alternativeembodiment, the metal layers 316 and 317, are formed of aluminum (Al).

As shown in FIG. 3, the floating gate 309 includes a vertical floatinggate 309 formed alongside of the body region 307. In the embodimentshown in FIG. 3, the control gate 313 includes a vertical control gate313 formed alongside of the vertical floating gate 309.

As will be explained in more detail below, the floating gate 309 andcontrol gate 313 orientation shown in FIG. 3 is just one embodiment fora vertical non volatile memory cell 300, according to the teachings ofthe present invention. In other embodiments, explained below, thefloating gate includes a horizontally oriented floating gate formedalongside of the body region. In this alternative embodiment, thecontrol gate includes a horizontally oriented control gate formed abovethe horizontally oriented floating gate.

FIG. 4 is a perspective view illustrating an array of silicon pillars400-1, 400-2, 400-3, . . . , 400-N, formed on a substrate 406 as used inone embodiment according to the teachings of the present invention. Aswill be understood by one of ordinary skill in the art upon reading thisdisclosure, the substrates can be (i) conventional p-type bulk siliconor p-type epitaxial layers on p+ wafers, (ii) silicon on insulatorformed by conventional SIMOX, wafer bonding and etch back or silicon onsapphire, or (iii) small islands of silicon on insulator.

As shown in FIG. 4, each pillar in the array of silicon pillars 400-1,400-2, 400-3, . . . , 400-N, includes a first source/drain region 401and a second source/drain region 403. The first and the secondsource/drain regions, 401 and 403, are separated by a body region 407including channel regions 405. As shown in FIG. 4, a number of trenches430 separate adjacent pillars in the array of silicon pillars 400-1,400-2, 400-3, . . . , 400-N. Trenches 430 are referenced in connectionwith the discussion which follows in connection with FIGS. 5A-5E.

FIGS. 5A-5E are cross sectional views taken along cut line 5-5 from FIG.4. As mentioned above in connection with FIG. 3, a number of floatinggate and control gate configurations are included in the presentinvention. FIG. 5A illustrates one such embodiment of the presentinvention. FIG. 5A illustrates a first source/drain region 501 andsecond source/drain region 503 for a DEAPROM memory cell 500 formedaccording to the teachings of the present invention. As shown in FIG. 5,the first and second source/drain regions, 501 and 503, are contained ina pillar of semiconductor material, and separated by a body region 507including channel regions 505. As shown in the embodiments of FIGS.5A-5E, the first source/drain region 501 is integrally connected to aburied sourceline 525. As one or ordinary skill in the art willunderstand upon reading this disclosure the buried sourceline 525 is beformed of semiconductor material which has the same doping type as thefirst source/drain region 501. In one embodiment, the sourceline 525 isformed of semiconductor material of the same doping as the firstsource/drain region 501, but is more heavily doped than the firstsource/drain region 501.

As shown in the embodiment of FIG. 5A, a pair of floating gates 509-1and 509-2 are formed in each trench 530 between adjacent pillars whichform memory cells 500-1 and 500-2. Each one of the pair of floatinggates, 509-1 and 509-2, respectively opposes the body regions 507-1 and507-2 in adjacent pillars 500-1 and 500-2 on opposing sides of thetrench 530.

In this embodiment, a single control gate 513 is shared by the pair offloating gates 509-1 and 509-2 on opposing sides of the trench 530. Asone of ordinary skill in the art will understand upon reading thisdisclosure, the shared single control gate 513 can include an integrallyformed control gate line. As shown in FIG. 5A, such an integrally formedcontrol gate line 513 can be one of a plurality of control gate lineswhich are each independently formed in the trench, such as trench 530,below the top surface of the pillars 500-1 and 500-2 and between thepair of floating gates 509-1 and 509-2. In one embodiment, according tothe teachings of the present invention, each floating gate, e.g. 509-1and 509-2, includes a vertically oriented floating gate having avertical length of less than 100 nanometers.

As shown in the embodiment of FIG. 5B, a pair of floating gates 509-1and 509-2 are formed in each trench 530 between adjacent pillars whichform memory cells 500-1 and 500-2. Each one of the pair of floatinggates, 509-1 and 509-2, respectively opposes the body regions 507-1 and507-2 in adjacent pillars 500-1 and 500-2 on opposing sides of thetrench 530.

In the embodiment of FIG. 5B, a plurality of control gate lines areagain formed in trenches, e.g. trench 530, below the top surface of thepillars, 500-1 and 500-2, and between the pair of floating gates 509-1and 509-2. However, in this embodiment, each trench, e.g. 530, houses apair of control gate lines, shown as 513-1 and 513-2. Each one of thepair of control gate lines 513-1 and 513-2 addresses the floating gates,509-1 and 509-2 respectively, on opposing sides of the trench 530. Inthis embodiment, the pair of control gate lines, or control gates 513-1and 513-2 are separated by an insulator layer.

As shown in the embodiment of FIG. 5C, a pair of floating gates 509-1and 509-2 are again formed in each trench 530 between adjacent pillarswhich form memory cells 500-1 and 500-2. Each one of the pair offloating gates, 509-1 and 509-2, respectively opposes the body regions507-1 and 507-2 in adjacent pillars 500-1 and 500-2 on opposing sides ofthe trench 530.

In the embodiment of FIG. 5C, the plurality of control gate lines aredisposed vertically above the floating gates. That is, in oneembodiment, the control gate lines are located above the pair offloating gates 509-1 and 509-2 and not fully beneath the top surface ofthe pillars 500-1 and 500-2. In the embodiment of FIG. 5C, each pair offloating gates, e.g. 509-1 and 509-2, in a given trench shares a singlecontrol gate line, or control gate 513.

As shown in the embodiment of FIG. 5D, a pair of floating gates 509-1and 509-2 are formed in each trench 530 between adjacent pillars whichform memory cells 500-1 and 500-2. Each one of the pair of floatinggates, 509-1 and 509-2, respectively opposes the body regions 507-1 and507-2 in adjacent pillars 500-1 and 500-2 on opposing sides of thetrench 530.

In the embodiment of FIG. 5D, the plurality of control gate lines aredisposed vertically above the floating gates. That is, in oneembodiment, the control gate lines are located above the pair offloating gates 509-1 and 509-2 and not fully beneath the top surface ofthe pillars 500-1 and 500-2. However, in the embodiment of FIG. 5D, eachone of the pair of floating gates, e.g. 509-1 and 509-2, is addressed byan independent one of the plurality of control lines or control gates,shown in FIG. 5D as 513-1 and 513-2.

As shown in the embodiment of FIG. 5E, a single floating gate 509 isformed in each trench 530 between adjacent pillars which form memorycells 500-1 and 500-2. According to the teachings of the presentinvention, the single floating gate 509 can be either a verticallyoriented floating gate 509 or a horizontally oriented floating gate 509formed by conventional processing techniques, or can be a horizontallyoriented floating gate 509 formed by replacement gate techniques. In oneembodiment of the present invention, the floating gate 509 has avertical length facing the body region 505 of less than 100 nm. Inanother embodiment, the floating gate 509 has a vertical length facingthe body region 505 of less than 50 nm. In one embodiment, as shown inFIG. 5E, the floating gate 509 is shared, respectively, with the bodyregions 507-1 and 507-2, including channel regions 505-1 and 505-2, inadjacent pillars 500-1 and 500-2 located on opposing sides of the trench530. And, as shown in FIG. 5E, the control gate includes a singlehorizontally oriented control gate line, or control gate 513 formedabove the horizontally oriented floating gate 509.

As one of ordinary skill in the art will understand upon reading thisdisclosure, in each of the embodiments described above in connectionwith FIGS. 5A-5E the floating gates 509 are separated from the controlgate lines, or control gates 513 with a low tunnel barrier intergateinsulator in accordance with the descriptions given above in connectionwith FIG. 3. That is, according to the teachings of the presentinvention, the low tunnel barrier intergate insulator has a thickness ofless than 20 Angstroms and/or a low tunnel barrier of less than 1.5 eV.The modifications here are to use tunneling through the interpolydielectric to realize DEAPROM memory devices which require refresh. Thevertical devices include an extra flexibility in that the capacitors,e.g. gate oxide and intergate insulator, are easily fabricated withdifferent areas. This readily allows the use of very high dielectricconstant inter-poly dielectric insulators with lower tunneling barriers.

FIGS. 6A-6D illustrate that a number of address coincidence schemes canbe used together with the present invention. FIG. 6A illustrates a NORDEAPROM memory array 610 having a number of DEAPROM memory cells 600-1,600-2, 600-3, using a coincidence address array scheme. For purposes ofillustration, FIG. 6A shows a sourceline 625 coupled to a firstsource/drain region 601 in each of the number of DEAPROM memory cells600-1, 600-2, 600-3. The sourceline is shown oriented in a firstselected direction in the DEAPROM memory array 610. In FIG. 6A, a numberof control gate lines 630 are shown oriented in a second selecteddirection in the DEAPROM memory array 610. As shown in FIG. 6A, thenumber of control gate lines 630 are coupled to, or integrally formedwith the control gates 613 for the number of DEAPROM memory cells 600-1,600-2, 600-3. As shown in FIG. 6A, the second selected direction isorthogonal to the first selected direction. Finally, FIG. 6A shows anumber of bitlines 635 oriented in a third selected direction in theDEAPROM memory array 610. As shown in FIG. 6A, the number of bitlinesare coupled to the second source/drain regions in the number of DEAPROMmemory cells 600-1, 600-2, 600-3. In the embodiment shown in FIG. 6A thethird selected direction is parallel to the second selected directionand the number of control gate lines 630 serve as address lines. Also,as shown in FIG. 6A, the DEAPROM memory array 610 includes a number ofbackgate or substrate/well bias address lines 640 coupled to thesubstrate.

Using FIG. 6A as a reference point, FIGS. 6B-6D illustrate of top viewfor three different coincidence address scheme layouts suitable for usewith the present invention. First, FIG. 6B provides the top view layoutof the coincidence address scheme described in connection with FIG. 6A.That is, FIG. 6B illustrates a number of sourcelines 625 oriented in afirst selected direction, a number of control gate lines 630 oriented ina second selected direction, and a number of bitlines 635 oriented in athird selected direction for the DEAPROM memory array 600. As explainedabove in connection with FIG. 6A, in this embodiment, the second andthird selected direction are parallel to one another and orthogonal tothe first selected direction such that the number of control gate lines630 serve as address lines.

FIG. 6C provides the top view layout of another coincidence addressscheme according to the teachings of the present invention. This is,FIG. 6C illustrates a number of sourcelines 625 oriented in a firstselected direction, a number of control gate lines 630 oriented in asecond selected direction, and a number of bitlines 635 oriented in athird selected direction for the DEAPROM memory array 600. In theembodiment of FIG. 6C, the first selected direction and the thirdselected direction are parallel to one another and orthogonal to thesecond selected direction. In this embodiment, the number of controlgate lines 630 again serve as address lines.

FIG. 6D provides the top view layout of yet another coincidence addressscheme according to the teachings of the present invention. This is,FIG. 6D illustrates a number of sourcelines 625 oriented in a firstselected direction, a number of control gate lines 630 oriented in asecond selected direction, and a number of bitlines 635 oriented in athird selected direction for the DEAPROM memory array 600. In theembodiment of FIG. 6D, the first selected direction and the secondselected direction are parallel to one another and orthogonal to thethird selected direction. In this embodiment, the number of bitlines 635serve as address lines.

As will be apparent to one of ordinary skill in the art upon readingthis disclosure, and as will be described in more detail below, writecan still be achieved by hot electron injection and/or, according to theteachings of the present invention, tunneling from the control gate.According to the teachings of the present invention, block erase isaccomplished by driving the control gates with a relatively largepositive voltage and tunneling from the metal on top of the floatinggate to the metal on the bottom of the control gate.

FIG. 7A is an energy band diagram illustrating the band structure atvacuum level with the low tunnel barrier interpoly insulator accordingto the teachings of the present invention. FIG. 7A is useful inillustrating the reduced tunnel barrier off of the floating gate to thecontrol gate and for illustrating the respective capacitances of thestructure according to the teachings of the present invention.

FIG. 7A shows the band structure of the silicon substrate, e.g. channelregion 701, silicon dioxide gate insulator, e.g. gate oxide 703,polysilicon floating gate 705, the low tunnel barrier interpolydielectric 707, between metal plates 709 and 711, and then thepolysilicon control gate 713, according to the teachings of the presentinvention. FIG. 7A illustrates the conventional silicon oxide gateinsulator 703 between the floating gate 705 and the channel region 701with a high barrier, e.g. 3.2 eV. FIG. 7A further illustrates the lowtunnel barrier interpoly insulator 707 between the floating gate 705 andthe control gate 713. According to the teachings of the presentinvention, if the interpoly dielectric 707 is thin enough, e.g. lessthan 20 Angstroms, or the barrier is low enough, e.g. less than 1.5 eV,to allow a very easy erase then there will be some finite leakagecurrent when the device is addressed for read operations and/or is in astandby state. Thus, according to the teachings of the presentinvention, this will require refresh of the memory state for theDEAPROM.

The design considerations involved are determined by the dielectricconstant, thickness and tunneling barrier height of the interpolydielectric insulator 707 relative to that of the silicon dioxide gateinsulator, e.g. gate oxide 703. The tunneling probability through theinterpoly dielectric 707 is an exponential function of both the barrierheight and the electric field across this dielectric.

FIG. 7B is an energy band diagram illustrating the band structure duringan erase operation of electrons from the floating gate 705 to thecontrol gate 713 across the low tunnel barrier interpoly insulator 707according to the teachings of the present invention. FIG. 7B issimilarly useful in illustrating the reduced tunnel barrier off of thefloating gate 705 to the control gate 713 and for illustrating therespective capacitances of the structure according to the teachings ofthe present invention.

As shown in FIG. 7B, the electric field is determined by the totalvoltage difference across the structure, the ratio of the capacitances(see FIG. 7A), and the thickness of the interpoly dielectric 707. Thevoltage across the interpoly dielectric 707 will be, ΔV2=V C1/(C1+C2),where V is the total applied voltage. The capacitances, C, of thestructures depends on the dielectric constant, ∈_(r), the permittivityof free space, e_(o), and the thickness of the insulating layers, t, andarea, A, such that C=∈_(r) ∈_(o) A/t, Farads/cm², where ∈_(r) representsthe low frequency dielectric constant. The electric field across theinterpoly dielectric insulator 707, having capacitance, C2, will then beE2=ΔV2/t2, where t2 is the thickness of this layer.

The tunneling current in erasing charge from the floating gate 705 bytunneling to the control gate 713 will then be as shown in FIG. 7B givenby an equation of the form: J = B  exp   (−Eo/E)$J = {\frac{q^{2}E^{2}}{4\pi\quad h\quad\Phi}{\mathbb{e}}^{{- E_{0}}/E}}$$E_{o} = {\frac{8\pi}{3}\frac{\sqrt{2m\overset{*}{q}}}{h}\Phi^{3/2}}$where E is the electric field across the interpoly dielectric insulator707 and Eo depends on the barrier height. Aluminum oxide which has acurrent density of 1 A/cm² at a field of about E=1V/20A=5×10⁺V/cm.Silicon oxide transistor gate insulators have a current density of 1A/cm² at a field of about E=2.3V/23A=1×10⁺⁷ V/cm.

The lower electric field in the aluminum oxide interpoly insulator 707for the same current density reflects the lower tunneling barrier ofless than 2.0 eV, shown in FIG. 7B, as opposed to the 3.2 eV tunnelingbarrier of silicon oxide 703, also illustrated in FIG. 7B. Low barriers,according to the teachings of the present invention, will result in highcurrent densities at low electric fields during write and erase,however, they will also conduct some small but significant currentduring the electric fields employed for read and as a consequence thedata must be refreshed. Thus, the DEAPROM devices of the presentinvention work on a dynamic basis.

FIG. 7C is a graph plotting tunneling currents versus the appliedelectric fields (reciprocal applied electric field shown) for a numberof barrier heights. FIG. 7C illustrates the dependence of the tunnelingcurrents on electric field (reciprocal applied electric field) andbarrier height. The fraction of voltage across the interpoly orintergate insulator, ΔV2, can be increased by making the area of theintergate capacitor, C2, (e.g. intergate insulator 707) smaller than thearea of the transistor gate capacitor, C1 (e.g. gate oxide 703). Thiswould be required with high dielectric constant intergate dielectricinsulators 707 and is easily realized with the vertical floating gatestructures described above in connection with FIGS. 3, and 5A-5E.

FIG. 8 is an energy band diagram illustrating work function, tunnelbarrier heights and electron affinities for a low tunnel barrierintergate insulator according to the teachings of the present invention.

Table A illustrates insulators of the order of 0.6 to 1.5 eV which areappropriate for use as the low tunnel barrier intergate insulator of thepresent invention. The values shown are for low tunnel barrier intergateinsulators selected from the group consisting of NiO, Al₂O₃, Ta₂O₅,TiO₂, ZrO₂, Nb₂O₅, Y₂O₃, Gd₂O₃, SrBi₂Ta₂O₃, SrTiO₃, PbTiO₃, and PbZrO₃.Also, as described above, the floating gate will include a polysiliconfloating gate having a metal layer formed thereon in contact with thelow tunnel barrier intergate insulator and the control gate will includea polysilicon control gate having a metal layer formed thereon incontact with the low tunnel barrier intergate insulator. In oneembodiment, the metal layers are formed of platinum (Pt). In analternative embodiment, the metal layers are formed of aluminum (Al).Thus, Table A illustrates the tunneling barrier values for the lowtunnel barrier intergate insulator formed between these respective metallayers. TABLE A E_(G) ε_(r) ε_(∞) χ Φ_(O)(Pt) Φ_(O)(Al) ConventionalInsulators SiO₂  ˜8 eV 4 2.25 0.9 eV 3.2 eV Si₃N₄  ˜5 eV 7.5 3.8 2.4 eVMetal Oxides Al₂O₃ 7.6 eV 9 to 11 3.4  ˜2 ev NiO Transition Metal OxidesTa₂O₅ 4.65-4.85 4.8 3.3 2.0 0.8 eV TiO₂ 6.8 30 7.8 3.9 Est. 80 1.2 eVZrO₂   5-7.8 18.5 4.8 2.5 1.4 25 Nb₂O₅ 3.1 35-50 Y₂O₃ 6   4.4 2.3 Gd₂O₃Perovskite Oxides SrBi₂Ta₂O₃ 4.1 5.3 3.3 2.0 0.8 eV SrTiO₃ 3.3 6.1 3.91.4 0.2 eV PbTiO₃ 3.4 6.25 3.5 1.8 0.6 eV PbZrO 3.7 4.8 Est. 0.2 eV 1.4eVMethods of Formation

Several examples are outlined below in order to illustrate how adiversity of such metal oxide tunnel barriers can be formed, accordingto the teachings of the present invention. Processing details andprecise pathways taken which are not expressly set forth below will beobvious to one of ordinary skill in the art upon reading thisdisclosure. Firstly, although not included in the details below, it isimportant also to take into account the following processing factors inconnection with the present invention:

(i) The poly-Si layer is to be formed with emphasis on obtaining asurface that is very smooth and morphologically stable at subsequentdevice processing temperatures which will exceed that used to grow Metaloxide.

(ii) The native SiO_(x) oxide on the poly-Si surface must be removed(e.g., by sputter cleaning in an inert gas plasma in situ) just prior todepositing the metal film. The electrical characteristics of theresultant Poly-Si/Metal/Metal oxide/Metal/Poly-Si structure will bebetter defined and reproducible than that of a Poly-Si/NativeSiO_(x)/Metal/Metal oxide/Poly-Si structure.

(iii) The oxide growth rate and limiting thickness will increase withoxidation temperature and oxygen pressure. The oxidation kinetics of ametal may, in some cases, depend on the crystallographic orientations ofthe very small grains of metal which comprise the metal film. If sucheffects are significant, the metal deposition process can be modified inorder to increase its preferred orientation and subsequent oxidethickness and tunneling uniformity. To this end, use can be made of thefact that metal films strongly prefer to grow during their depositionshaving their lowest free energy planes parallel to the film surface.This preference varies with the crystal structure of the metal. Forexample, fcc metals prefer to form {111} surface plans. Metalorientation effects, if present, would be larger when only a limitedfraction of the metal will be oxidized and unimportant when all or mostof the metal is oxidized.

(iv) Modifications in the structure shown in FIG. 2 may be introduced inorder to compensate for certain properties in some metal/oxide/metallayers. Such changes are reasonable since a wide range of metals, alloysand oxides with quite different physical and chemical properties can beused to form these tunnel junctions.

EXAMPLE I Formation of Al₂O₃ or NiO Tunnel Barriers

As stated above, the conventional large barrier insulating dielectricsare silicon oxide and silicon nitride. The realities are that siliconoxide is not an optimum choice for memory type devices, because the 3.2eV tunnel barrier is too high resulting in premature failure of theinsulators and limiting the number of operational cycles to be in theorder of 10⁵ to 10⁷.

According to one embodiment of the present invention, a low tunnelingbarrier interpoly insulator is used instead, such as Al₂O₃ or NiO havinga thickness of less than 20 Angstroms so that the tunneling barrier isless than 1.5 eV. A number of studies have dealt with electron tunnelingin Al/Al₂O₃/Al structures where the oxide was grown by “low temperatureoxidation” in either molecular or plasma oxygen. Before sketching out aprocessing sequence for these tunnel barriers, note:

(i) Capacitance and tunnel measurements indicate that the Al₂O₃thickness increases with the log (oxidation time), similar to that foundfor PbO/Pb as well as a great many other oxide/metal systems.

(ii) Tunnel currents are asymmetrical in this system with somewhatlarger currents flowing when electrons are injected from the Al/Al₂O₃interface developed during oxide growth. This asymmetry is due to aminor change in composition of the growing oxide: there is a smallconcentration of excess metal in the Al₂O₃, the concentration of whichdiminishes as the oxide is grown thicker. The excess Al⁺³ ions produce aspace charge that lowers the tunnel barrier at the inner interface. Theoxide composition at the outer Al₂O₃/Al contact is much morestoichiometric and thus has a higher tunnel barrier. In situellipsometer measurements on the thermal oxidation of Al films depositedand oxidized in situ support this model. In spite of this minorcomplication, Al/Al₂O₃/Al tunnel barriers can be formed that willproduce predictable and highly controllable tunnel currents that can beejected from either electrode. The magnitude of the currents are stillprimarily dominated by Al₂O₃ thickness which can be controlled via theoxidation parametrics.

With this background, we can proceed to outline one process path out ofseveral that can be used to form Al₂O₃ tunnel barriers. Here thealuminum is thermally oxidized although one could use other techniquessuch as plasma oxidation or rf sputtering in an oxygen plasma. For thesake of brevity, some details noted above will not be repeated.

(i) Sputter deposit aluminum on poly-Si at a temperature of ˜25 to 150degrees C. Due to thermodynamic forces, the micro-crystallites of thef.c.c. aluminum will have a strong and desirable (111) preferredorientation.

(ii) Oxidize the aluminum in situ in molecular oxygen usingtemperatures, pressure and time to obtain the desired Al₂O₃ thickness.The thickness increases with log (time) and can be controlled via timeat a fixed oxygen pressure and temperature to within 0.10 Angstroms,when averaged over a large number of aluminum grains that are presentunder the counter-electrode. One can readily change the Al₂O₃ thicknessfrom ˜15 to 35Å by using appropriate oxidation parametrics. The oxidewill be amorphous and remain so until temperatures in excess of 400degrees C. are reached. The initiation of recrystallization and graingrowth can be suppressed, if desired, via the addition of small amountsof glass forming elements (e.g., Si) without altering the growthkinetics or barrier heights significantly.

(iii) Re-evacuate the system and deposit a second layer of aluminum.

(iv) Deposit the Poly-Si control gate layer using conventionalprocesses.

In an alternative embodiment, nickel (Ni) can be oxidized to form thinsuper-conducting tunnel diodes or tunneling magnetoresistive elements.

As mentioned above, these oxide insulators are used as low tunnelbarriers, of the order 0.6 to 1.5 eV, as the inter-poly or inter-gatedielectric insulators. The characteristics of these oxide insulators arealso summarized in Table A. According to the teachings of the presentinvention, low barriers are utilized in dynamic memory elements whichare easy to write and/or erase but as a consequence of the low barrierrequire refresh. To achieve the correct barrier height different contactmetals as for instance aluminum (Al) and platinum (Pt) may be used asillustrated in FIGS. 2 and 3. That is according to the teachings of thepresent invention the floating gate includes a polysilicon floating gatehaving a metal layer formed thereon in contact with the low tunnelbarrier intergate insulator. Likewise, as described above the controlgate includes a polysilicon control gate having a metal layer formedthereon in contact with the low tunnel barrier intergate insulator. Inone embodiment, the metal layers are formed of platinum (Pt). In analternative embodiment, the metal layers are formed of aluminum (Al).FIG. 9 illustrates the tunneling barrier values for the Al₂O₃ and NiOintergate insulator embodiments formed between these respective metallayers. In conjunction with these embodiments of the invention, the lowtunnel barrier interpoly insulator is formed with a thickness of lessthan 20 Angstroms such that the tunnel barrier is less than 1.5 eV.

EXAMPLE II Formation of Single- and Multi-Layer Transition Metal OxideTunnel Barriers

The band gap energies and barrier heights of some conventional gateinsulators as silicon oxide, silicon nitride and aluminum oxide as wellas tantalum oxide have been investigated and described in detail.Formation of single and double-layer dielectric layers of oxides ofTa₂O₅ and similar transition metal oxides can be accomplished by thermalas well as plasma oxidation of films of these metals.

In some cases the characteristics of the resulting dielectric insulatorsare not yet well known or well defined. Part of this detail is recountedas follows.

For example, single layers of Ta₂O₅, TiO₂, ZrO₂, Nb₂O₅ and similartransition metal oxides can be formed by “low temperature oxidation” ofnumerous Transition Metal (e.g., TM oxides) films in molecular andplasma oxygen and also by rf sputtering in an oxygen plasma. The thermaloxidation kinetics of these metals have been studied for decades. Inessence, such metals oxidize via logarithmic kinetics to reachthicknesses of a few to several tens of angstroms in the range of 100 to300C. Excellent oxide barriers for Josephson tunnel devices can beformed by rf sputter etching these metals in an oxygen plasma. Such “lowtemperature oxidation” approaches differ considerably from MOCVDprocesses used to produce these TM oxides. MOCVD films require hightemperature oxidation treatments to remove carbon impurities, improveoxide stoichiometry and produce recrystallization. Such high temperaturetreatments also cause unwanted interactions between the oxide and theunderlying silicon and thus have necessitated the introduction ofinterfacial barrier layers.

An approach was developed utilizing “low temperature oxidation” to formduplex layers of TM oxides. Unlike MOCVD films, the oxides are very pureand stoichiometric as formed. They do require at least a brief hightemperature (est. 700 to 800 degrees C. but may be lower) treatment totransform their microstructures from amorphous to crystalline and thusincrease their dielectric constants to the desired values (>20 or so).Unlike MOCVD oxides, this treatment can be carried out in an inert gasatmosphere, thus lessening the possibility of inadvertently oxidizingthe poly-Si floating gate. While this approach was directed atdeveloping methods and procedures for producing high dielectric constantfilms for storage cells for DRAMs, the same teachings can be applied toproducing thinner metal oxide tunnel films for DEAPROM memory devicesdescribed. The dielectric constants of these TM oxides are substantiallygreater (>25 to 30 or more) than those of PbO and Al₂O₃. Duplex layersof these high dielectric constant oxide films are easily fabricated withsimple tools and also provide improvement in device yields andreliability. Each oxide layer will contain some level of defects but theprobability that such defects will overlap is exceedingly small. Effectsof such duplex layers were first reported by one of the present authors,J. M. Eldridge, and are well known to practitioners of the art. It isworth mentioning that highly reproducible TM oxide tunnel barriers canbe grown by rf sputtering in an oxygen ambient. Control over oxidethickness and other properties in these studies were all the moreremarkable in view of the fact that the oxides were typically grown onthick (e.g., 5,000 Å) metals such as Nb and Ta. In such metal-oxidesystems, a range of layers and suboxides can also form, each havingtheir own properties. In the present disclosure, control over theproperties of the various TM oxides will be even better since we employvery limited thicknesses of metal (perhaps 10 to 100 Å or so) andthereby preclude the formation of significant quantities of unwanted,less controllable sub-oxide films. Thermodynamic forces will drive theoxide compositions to their most stable, fully oxidized state, e.g.,Nb₂O₅, Ta₂O₅, etc. As noted above, it will still be necessary tocrystallize these duplex oxide layers. Such treatments can be done byRTP and will be shorter than those used on MOCVD and sputter-depositedoxides since the stoichiometry and purity of the “low temperatureoxides” need not be adjusted at high temperature.

Although perhaps obvious to those skilled in the art, one can sketch outa few useful fabrication guides:

(i) Thinner TM layers will be used in this invention relative to thoseused to form DRAMs. Unlike DRAMs where leakage must be eliminated, theduplex oxides used here must be thin enough to carry very controlledlevels of current flow when subjected to reasonable applied fields andtimes.

(ii) The TM and their oxides are highly refractory and etchable (e.g.,by RIE). Hence they are quite compatible with poly-Si control gateprocesses and other subsequent steps.

(iii) TM silicide formation will not occur during the oxidation step. Itcould take place at a significant rate at the temperatures used todeposit the poly-Si control gate. If so, several solutions can beapplied including:

-   -   (i) Insert certain metals at the TM/poly-Si boundaries that will        prevent inter-diffusion of the TM and the poly-Si.    -   (ii) Completely oxide the TMs. The electrical characteristics of        the resulting poly-Si/TM oxide 1/TM oxide 2/poly-Si structure        will be different in the absence of having TM at the oxide/metal        interfaces.

Insulator and contact metal layer combinations, e.g. platinum (Pt) andaluminum (Al) with appropriate barrier heights, according to theteachings of the present invention, have been circled in FIG. 9. Also,as described above, the transition metal oxide interpoly insulators canbe formed having a thickness of less than 20 Angstroms such that thetunnel barrier is less than 1.5 eV as required by the present invention.

EXAMPLE III Formation of Alternate Metal Compound Tunnel Barriers

Although no applications may be immediately obvious, it is conceivablethat one might want to form a stack of oxide films having quitedifferent properties, for example, a stack comprised of a highdielectric constant (k) oxide/a low k oxide/a high k oxide. “Lowtemperature oxidation” can be used to form numerous variations of suchstructures. While most of this disclosure deals with the formation anduse of stacks of oxide dielectrics, it is also possible to use “lowtemperature oxidation” to form other thin film dielectrics such asnitrides, oxynitrides, etc. that could provide additional functions suchas being altered by monochromatic light, etc. These will not bediscussed further here.

EXAMPLE IV Formation of Perovskite Oxide Tunnel Barriers

Oxide tunnel barriers having a wide range of properties can also begrown via oxidation of alloy films of appropriate compositions. Thinfilm barriers of platinum, palladium and similar noble metals must beadded to prevent inter-diffusion and degradation of the perovskiteoxides with the poly-Si layers. Some processing remarks are statedbelow.

For example, results have been obtained which demonstrate that at leasta limited range of high temperature, super-conducting oxide films can bemade by thermally oxidizing Y—Ba—Cu alloy films. “Low temperatureoxidation” and short thermal treatments in an inert ambient at 700C inorder to form a range of perovskite oxide films from parent alloy filmshave also been employed. The dielectric constants of crystallized,perovskite oxides can be very large, with values in the 100 to 1000 ormore range. The basic process is more complicated than that needed tooxidize layered films of transition metals. (See Example II.) The TMlayers would typically be pure metals although they could be alloyed.The TMs are similar metallurgically as are their oxides. In contrast,the parent alloy films that can be converted to a perovskite oxide aretypically comprised of metals having widely different chemicalreactivities with oxygen and other common gasses. In the Y—Ba—Cu systemreferenced above, Y and Ba are among the most reactive of metals whilethe reactivity of Cu approaches (albeit distantly) those of other noblemetals. If the alloy is to be completely oxidized, then thin filmbarriers such as Pd, Pt, etc. or their conductive oxides must be addedbetween the Si and the parent metal film to serve as: electrical contactlayers; diffusion barriers; and, oxidation stops. In such a case, theSchottky barrier heights of various TM oxides and perovskite oxides incontact with various metals will help in the design of the tunneldevice. In the more likely event that the perovskite parent alloy filmwill be only partially converted to oxide and then covered with a secondlayer of the parent alloy (recall the structure of FIG. 2), then thebarrier heights will represent that developed during oxide growth at theparent perovskite alloy/perovskite oxide interface. Obviously, suchbarrier heights cannot be predicted ab initio for such a wide class ofmaterials but will have to be developed as the need arises. Thisinformation will have to be developed on a system-by-system basis.

System Level

FIG. 9 illustrates a block diagram of an embodiment of an electronicsystem 901 according to the teachings of the present invention. In theembodiment shown in FIG. 9, the system 901 includes a memory device 900which has an array of memory cells 902, address decoder 904, row accesscircuitry 906, column access circuitry 908, control circuitry 910, andinput/output circuit 912. Also, as shown in FIG. 9, the circuit 901includes a processor 914, or memory controller for memory accessing. Thememory device 900 receives control signals from the processor 914, suchas WE*, RAS* and CAS* signals over wiring or metallization lines. Thememory device 900 is used to store data which is accessed via I/O lines.It will be appreciated by those skilled in the art that additionalcircuitry and control signals can be provided, and that the memorydevice 900 has been simplified to help focus on the invention. At leastone of the memory cells 902 has a memory cell formed according to theembodiments of the present invention. That is, at least one memory cellincludes a low tunnel barrier interpoly insulator according to theteachings of the present invention.

It will be understood that the embodiment shown in FIG. 9 illustrates anembodiment for electronic system circuitry in which the novel memorycells of the present invention are used. The illustration of system 901,as shown in FIG. 9, is intended to provide a general understanding ofone application for the structure and circuitry of the presentinvention, and is not intended to serve as a complete description of allthe elements and features of an electronic system using the novel memorycell structures. Further, the invention is equally applicable to anysize and type of memory device 901 using the novel memory cells of thepresent invention and is not intended to be limited to that describedabove. As one of ordinary skill in the art will understand, such anelectronic system can be fabricated in single-package processing units,or even on a single semiconductor chip, in order to reduce thecommunication time between the processor and the memory device.

Applications containing the novel memory cell of the present inventionas described in this disclosure include electronic systems for use inmemory modules, device drivers, power modules, communication modems,processor modules, and application-specific modules, and may includemultilayer, multichip modules. Such circuitry can further be asubcomponent of a variety of electronic systems, such as a clock, atelevision, a cell phone, a personal computer, an automobile, anindustrial control system, an aircraft, and others.

Method of Operation

Write can be achieved by tunneling from the control gate by driving thecontrol gate negative and/or channel hot electron injection as in flashmemory devices. Erase would be accomplished by driving the control gateswith a relatively large positive voltage and tunneling from the metal ontop of the floating gate to the metal on the bottom of the control gate.Read is accomplished by driving the control gate with a smaller positivevoltage, if no electrons are stored on the floating gate the transistorwill turn on. If electrons are stored on the floating gate thetransistor will not turn on or only turn on at a lower conductivitystate, this constitutes the memory function.

During a read operation the control gate is driven with the samepositive polarity voltage that is used for erase. A low tunnel barrierbetween the floating gate and the control gate will make the eraseoperation easy but will also result in some finite leakage current atthe lower positive control gate voltage during read. If as in DRAMs aretention time of one second is required then the leakage current at theread voltage must be small. If the gate oxide is 2 nm (20 Å) thick thenthe capacitance is about 1.6×10⁻⁶ F/cm² and a 1 Volt difference willstore a charge of 1.6×10⁻⁶ Coulombs/cm². A retention time of one secondrequires a leakage current of less than about 10⁻⁶ Amps/cm²; as shown inFIG. 7C if the tunneling barrier is 1.25 eV and the electric field inthe low barrier interpoly/intergate insulator is less than about 1.5×10⁶V/cm then this will be achieved. On the other hand, if during erase theelectric field in the interpoly/intergate insulator is over 2.5×10⁶ V/cmthen the erase current will be over 1 Amp/cm² and erase will be easilyachieved in less than a microsecond. The lower tunneling barrier, 1.25eV, results in a much faster erase at much lower electric fields andthan in conventional flash memory devices which require fields of 10⁷V/cm to achieve the same erase current of 1 Amp/cm² with a silicon oxidetunnel barrier of 3.2 eV.

The high electric fields in conventional flash memory devices result inpremature insulator failures and reliability failures since theseelectric fields are very close to the dielectric strength of the siliconoxide gate insulators. Here the tunnel barriers are very low in theorder of 0.6 to 1.5 eV, while this makes the erase very easy on theother hand the finite leakage currents require that these memory devicesbe refreshed, in other words they emulate DRAMs.

CONCLUSIONS

Low barrier tunnel insulators are described between the floating gateand control gate in a flash memory type devices to form DEAPROM cellswhich require refresh. These low barrier insulators, 1.5-0.6 eV, areeasily fabricated by the oxidation of a transition metal or a compositemetal layer. The devices work on a dynamic basis and must be refreshed,in this respect they emulate DRAM's. While the amount of charge storedon the floating gate is small the transistor provides gain and chargemultiplication resulting in a large output signal and ease of readingthe stored data. If there is an adverse capacitance ratio due to a largedifference of dielectric constants then the vertical gate structuresdescribed previously can be employed.

Write can be achieved by the normal channel hot electron injection andgate current through the silicon oxide to the floating gate. This isdone by selecting a particular column by applying a high control gatevoltage and applying relatively large drain voltage as is done withconventional ETOX memory devices. However, according to the teachings ofthe present invention, write can also be accomplished by applying apositive voltage to the substrate or well select line and a largenegative voltage to the control gates, electrons will tunnel from thecontrol gate to the floating gate. The low tunnel barrier will providean easy write operation and the selection of the substrate or well biaswill provide selectivity and address only one device.

According to the teachings of the present invention, erase is achievedby providing a negative voltage to the substrate or well address lineand a large positive voltage to the control gate. This causes electronsto tunnel off of the floating gate on to the control gate. A whole rowcan be erased by addressing all the column lines along that row and ablock can be erased by addressing multiple row back gate orsubstrate/well address lines.

Read is accomplished as in conventional ETOX memory devices. A columnline is addressed by applying a positive control gate voltage andsensing the current along the data bit or drain row address line.

The above structures and fabrication methods have been described, by wayof example, and not by way of limitation, with respect to DEAPROM memorywith low tunnel barrier interpoly insulators.

It has been shown that the low tunnel barrier interpoly insulators ofthe present invention avoid the large barriers to electron tunneling orhot electron injection presented by the silicon oxide-silicon interface,3.2 eV, which result in slow write and erase speeds even at very highelectric fields. The present invention also avoids the combination ofvery high electric fields and damage by hot electron collisions in thewhich oxide result in a number of operational problems like soft eraseerror, reliability problems of premature oxide breakdown and a limitednumber of cycles of write and erase. Further, the low tunnel barrierinterpoly dielectric insulator erase approach, of the present inventionremedies the above mentioned problems of having a rough top surface onthe polysilicon floating gate which results in, poor quality interpolyoxides, sharp points, localized high electric fields, prematurebreakdown and reliability problems.

The above mentioned problems with DEAPROM memories and other problemsare addressed by the present invention and will be understood by readingand studying the specification. Systems and methods are provided formemories, such as DEAPROM, with metal oxide and/or low tunnel barrierinterpoly insulators which require refresh. That is, the presentinvention describes the use of an ultra-thin metal oxide inter-polydielectric insulators between the control gate and the floating gate tocreate a memory cell which has a high current gain, and is easy toprogram by tunneling but which requires refresh. The low barrier tunnelinsulator between the floating gate and control gates makes erase of thecell easy but results in the requirement for refresh. These devices actlike DRAM's and can be utilized as DRAM replacements. A coincidentaddress is achieved by addressing both the control gate address lines(y-address) and source address lines (x-address).

In one embodiment of the present invention, the memory includes a firstsource/drain region and a second source/drain region separated by achannel region in a substrate. A floating gate opposing the channelregion and is separated therefrom by a gate oxide. A control gateopposes the floating gate. The control gate is separated from thefloating gate by a low tunnel barrier intergate insulator having atunnel barrier of less than 1.5 eV. The low tunnel barrier intergateinsulator includes a metal oxide insulator selected from the groupconsisting of NiO, Al₂O₃, Ta₂O₅, TiO₂, ZrO₂, Nb₂O₅, Y₂O₃, Gd₂O₃,SrBi₂Ta₂O₃, SrTiO₃, PbTiO₃, and PbZrO₃. The floating gate includes apolysilicon floating gate having a metal layer formed thereon in contactwith the low tunnel barrier intergate insulator. And, the control gateincludes a polysilicon control gate having a metal layer formed thereonin contact with the low tunnel barrier intergate insulator.

These and other embodiments, aspects, advantages, and features of thepresent invention will be set forth in part in the description, and inpart will become apparent to those skilled in the art by reference tothe description of the invention and referenced drawings or by practiceof the invention. The aspects, advantages, and features of the inventionare realized and attained by means of the instrumentalities, procedures,and combinations particularly pointed out in the appended claims.

DOCUMENTS

-   application Ser. No. 09/945,507, L. Forbes and J. M. Eldridge,    “FLASH MEMORY DEVICES WITH METAL OXIDE INTERPOLY INSULATORS,”    attorney docket no. 1303.014us1, filed Aug. 30, 2001;-   application Ser. No. 08/902,843, “DEAPROM (Dynamically Electrically    Alterable Programmable Read Only Memory) UTILIZING INSULATING AND    AMORPOHOUS SILICON CARBIDE GATE INSULATOR,” filed Jul. 29, 1997;-   S. R. Pollack and C. E. Morris, “Tunneling through gaseous oxidized    films of AL2O3,” Trans. AIME, Vol. 233, p. 497, 1965;-   Y. Shi et al., “Tunneling leakage current in ultrathin (<4 nm)    nitride/oxide stack dielectrics,” IEEE Electron Device Letters, Vol.    19, No. 10, pp. 388-390, 1998;-   U.S. Pat. No. 6,134,175, “Memory Address Decode Array with vertical    transistors;”-   U.S. Pat. No. 5,691,230, “Technique for Producing Small Islands of    Silicon on Insulator;”-   U.S. Pat. No. 6,424,001, “Flash Memory with Ultrathin Vertical Body    Transistors;” O. Kubaschewski and B. E. Hopkins, “Oxidation of    Metals and Alloys,” Butterworth, London, pp/53-64, 1962;-   S. M. Sze, “Physics of Semiconductor Devices,” Wiley, NY, pp.    553-556, 1981;-   J. Simmons and A. El-Badry, “Generalized formula for the electric    tunnel effect between similar electrodes separated by a thin    insulating film,” J. Appl. Phys., Vol. 34, p. 1793, 1963;-   Z. Hurych, “Influence of nonuniform thickness on dielectric layers    on capacitance and tunnel currents,” Solid-State Electronics, Vol.    9, p. 967, 1966;-   S. P. S. Arya and H. P. Singh, “Conduction properties of thin Al₂O₃    films,” Thin Solid Films, Vol. 91, No. 4, pp. 363-374, May 1982;-   K.-H. Gundlach and J. Holzl, “Logarithmic conductivity of    Al—Al₂O₃-AL tunneling junctions produced by plasma- and by    thermal-oxidation,” Surface Science, Vol. 27, pp. 125-141, 1971;-   J. M. Grimblot and J. M. Eldridge, “I. Interaction of Al films with    O₂ at low pressures,” J. Electro. Chem. Soc., Vol. 129, No. 10, pp.    2366-2368, 1982;-   J. Grimblot and J. M. Eldridge, “II. Oxidation of Al films,” J.    Electro. Chem. Soc., Vol. 129, No. 10, pp. 2369-2372, 1982;-   J. H. Greiner, “Oxidation of lead films by rf sputter etching in an    oxygen plasma,” J. Appl. Phys., vol. 45, No. 1, pp. 32-37, 1974;-   R. G. Marchalek et al., “Photoresponse characteristics of    thin-filmed nickel-nickel oxide-nickel tunnel junctions,” IEEE    Journal of Quantum Electronics, Vol. QE-1, No. 4, pp. 743-754, April    1983;-   L. Eierdal et al., “Interaction of oxygen with Ni(110) studied by    scanning tunneling Microscopy,” Surface Science, Vol. 312, No. 1-2,    pp. 31-53, Jun. 1, 1994;-   H. Itokawa et al., “Determination of bandgap and energy band    alignment for high-dielectric-constant gate insulators using    high-resolution x-ray photoelectron spectroscopy,” Ext. Abstracts    Int. Conf. On Solid State Devices and Materials, pp. 158-159, 1999;-   H. F. Luan et al., “High Quality Ta2O5 gate dielectrics with Tox,    eq<10 Å,” International Electron Devices Meeting Technical digest,    pp. 141-144, 1999;-   J. Robertson and C. W. Chen, “Schottky barrier heights of tantalum    oxide, barium strontium titanate, lead titanate, and strontium    bismuth tantalite,” Appl. Phys. Lett., Vol. 74, No. 8, pp.    1168-1170, Feb. 22, 1999;-   J. Robertson, “Band offsets of wide-band gap oxides and implications    for future electronic devices,” J. Vac. Sci. Technol., Vol. B 18,    No. 3, pp. 1785-1794, May-June 2000;-   X. Guo et al., “High Quality ultra-thin (1.5 nm) TiO2/Si3N4 gate    dielectric for deep submicron CMOS technology,” International    Electron Devices Meeting Technical Digest, pp. 137-140, 1999;-   H. Kim et al., “Leakage current and electrical breakdown in    metal-organic chemical vapor deposited TiO2 dielectrics on silicon    substrates,” Vol. 69, No. 25, pp. 3860-3862, Dec. 16, 1996;-   J. Yan et al., “Structure and electrical characterization of TiO2    grown from titanium tetrakis-isoproxide (TTIP) and TTIP/H₂O    ambient,” J. Vac. Sci. Technol., Vol. B 14, No. 3, pp. 1706-1711,    1996;-   W. Qi et al., “MOSCAP and MOSFET characteristics using ZrO2 gate    dielectric deposited directly on Si,” Technical Digest of 1999 IEDM,    pp. 145-148;-   Y. Ma et al., “Zirconium Oxide Band Gate Dielectrics with Equivalent    Oxide and Thickness of Less Than 1.0 nm and Performance of    Sub-micron MOSFET using a Nitride Gate Replacement Process,” Digest    of 1999 IEDM, pp. 149-152;-   Afanas et al., “Electron energy barriers between (100) Si and    ultrathin stacks of SiO2, AL2O3, and ZrO2 insulators,” Appl. Phys.    Lett., Vol. 78, No. 20, pp. 3073-3075, 2001;-   K. Kukli et al., “Development of dielectric properties of niobium    oxide, tantalum oxide, and aluminum oxide based nanolayered    materials,” J. Electro. Chem. Soc., Vol. 148, No. 2, pp. F35-F41,    2001;-   J. Kwo et al., “Properties of high k gate dielectrics Gd2O3 and Y2O    for Si,” J. Appl. Phys., Vol. 89, No. 7, pp. 3920-3927, 2001;-   J. M. Greiner, “Josephson tunneling barriers by rf sputter etching    in an oxygen plasma,” J. Appl. Phys., Vol. 42, No. 12, pp.    5151-5155, 1971;-   U.S. Pat. No. 4,412,902, “Method of fabrication of Josephson tunnel    junctions;”-   U.S. Pat. No. 6,461,931, “Thin dielectric films for DRAM storage    capacitors”; and-   U.S. Pat. No. 5,350,738, “Method of manufacturing an oxide    superconducting film.”    The above documents are incorporated by reference for any purpose.

1. A floating gate transistor, comprising: a first source/drain regionand a second source drain region spaced apart from the firstsource/drain region; a channel region interposed between the firstsource drain/region and the second source/drain region; a floating gatestructure positioned proximate to the channel region and spaced apartfrom the channel region by a gate oxide layer; and a control gatestructure positioned proximate to the floating gate structure andseparated from the floating gate structure by a low tunnel barrierintergate dielectric layer having a tunnel barrier of less thanapproximately 1.5 eV.
 2. The floating gate transistor of claim 1,wherein the low tunnel barrier intergate dielectric layer furthercomprises one of a selected oxide of nickel and a selected oxide ofaluminum.
 3. The floating gate transistor of claim 1, wherein the lowtunnel barrier intergate dielectric layer further comprises a selectedoxide of a transition metal.
 4. The floating gate transistor of claim 3,wherein the selected oxide of a transition metal comprises a selectedoxide of tantalum, titanium, zirconium, niobium, yttrium and gadolinium.5. The floating gate transistor of claim 1, wherein the low tunnelbarrier intergate dielectric layer further comprises a perovskitematerial.
 6. The floating gate transistor of claim 5, wherein theperovskite material comprises at least one of SrBi₂Ta₂O₃, SrTiO₃, PbTiO₃and PbZrO₃.
 7. The floating gate transistor of claim 1, wherein the lowtunnel barrier intergate dielectric layer further comprises a low tunnelbarrier intergate dielectric layer having a thickness of less thanapproximately 20 Angstroms.
 8. The floating gate transistor of claim 1,wherein the first source/drain region and the second source/drain regionfurther comprise an n-doped region.
 9. The floating gate transistor ofclaim 1, further comprising a first metal layer adjacent the floatinggate structure and a second metal layer adjacent the control gatestructure so that the a low tunnel barrier intergate dielectric layer ispositioned between the first metal layer and the second metal layer. 10.The floating gate transistor of claim 9, wherein the first metal layerand the second metal layer further comprise one of a platinum layer andan aluminum layer.
 11. The floating gate transistor of claim 1, whereinthe floating gate structure and the control gate structure are comprisedof polysilicon.
 12. The floating gate transistor of claim 1, wherein thefirst source/drain region is coupled to a source line of the memorydevice, the second source/drain layer is coupled to a bit line of thememory device, and the control gate is coupled to a control line of thememory device.
 13. A memory cell for a non-volatile memory device,comprising: a first source/drain region and a second source drain regionspaced apart from the first source/drain region; a channel regionpositioned between the first source drain/region and the secondsource/drain region; a polysilicon floating gate structure positionedproximate to the channel region and spaced apart from the channel regionby a gate oxide layer; a polysilicon control gate structure positionedproximate to the polysilicon floating gate structure; and a low tunnelbarrier intergate dielectric layer having a tunnel barrier of less thanapproximately 1.5 eV that is positioned between the polysilicon floatinggate structure and the polysilicon control gate structure, wherein thelow tunnel barrier intergate dielectric layer includes metal layersformed on opposing sides of the intergate dielectric layer.
 14. Thememory cell of claim 13, wherein the low tunnel barrier intergatedielectric layer further comprises one of a nickel oxide dielectriclayer and an aluminum oxide dielectric layer.
 15. The memory cell ofclaim 13, wherein the low tunnel barrier intergate dielectric layerfurther comprises a transition metal oxide layer.
 16. The memory cell ofclaim 15, wherein the transition metal oxide layer comprises a selectedoxide of tantalum, titanium, zirconium, niobium, yttrium and gadolinium.17. The memory cell of claim 13, wherein the low tunnel barrierintergate dielectric layer further comprises a layer of a perovskitematerial, including one of SrBi₂Ta₂O₃, SrTiO₃, PbTiO₃ and PbZrO₃. 18.The memory cell of claim 13, wherein the low tunnel barrier intergatedielectric layer further comprises a low tunnel barrier intergatedielectric layer having a thickness of less than approximately 20Angstroms.
 19. The memory cell of claim 13, wherein the metal layersfurther comprise one of a platinum layer and an aluminum layer.
 20. Thememory cell of claim 13, wherein the first source/drain region iscoupled to a source line of the memory device, the second source/drainlayer is coupled to a bit line of the memory device, and the controlgate is coupled to a control line of the memory device.
 21. A memorystructure for a non-volatile memory device, comprising: a plurality ofmemory cells arranged in an array, wherein at least one of the pluralityof memory cells further comprises: a first source/drain region and asecond source drain region spaced apart from the first source/drainregion; a channel region interposed between the first sourcedrain/region and the second source/drain region; a floating gatestructure positioned proximate to the channel region and spaced apartfrom the channel region by a gate oxide layer; a control gate structurepositioned proximate to the floating gate structure; and a low tunnelbarrier intergate dielectric layer having a tunnel barrier of less thanapproximately 1.5 eV that is positioned between the polysilicon floatinggate structure and the polysilicon control gate structure, wherein asource line of the array is coupled to the first source/drain region, abit line of the array is coupled to the second source/drain layer, and acontrol line of the array is coupled to the control gate.
 22. The memorystructure of claim 21, wherein the low tunnel barrier intergatedielectric layer further comprises one of a nickel oxide dielectriclayer and an aluminum oxide dielectric layer.
 23. The memory structureof claim 21, wherein the low tunnel barrier intergate dielectric layerfurther comprises a transition metal oxide layer.
 24. The memorystructure of claim 23, wherein the transition metal oxide layercomprises a selected oxide of tantalum, titanium, zirconium, niobium,yttrium and gadolinium.
 25. The memory structure of claim 21, whereinthe low tunnel barrier intergate dielectric layer further comprises alayer of a perovskite material.
 26. The memory structure of claim 25,wherein the layer of a perovskite material comprises at least one ofSrBi₂Ta₂O₃, SrTiO₃, PbTiO₃ and PbZrO₃.
 27. The memory structure of claim21, wherein the low tunnel barrier intergate dielectric layer furthercomprises a low tunnel barrier intergate dielectric layer having athickness of less than approximately 20 Angstroms.
 28. The memorystructure of claim 21, further comprising a first metal layer adjacentthe floating gate structure and a second metal layer adjacent thecontrol gate structure so that the a low tunnel barrier intergatedielectric layer is positioned between the first metal layer and thesecond metal layer.
 29. The memory structure of claim 28, wherein thefirst metal layer and the second metal layer further comprise one of aplatinum layer and an aluminum layer.
 30. The memory structure of claim21, wherein the floating gate structure and the control gate structureare comprised of polysilicon.